Muting circuit

ABSTRACT

Disclosed is a muting circuit, in which the generation of click noise is prevented in that the muting operation is caused to occur at an instant when the instantaneous level (i.e., waveform level) of the input audio signal becomes zero for the first time since the appearance of a muting signal. .Iadd.A muting-off circuit is also disclosed for turning off the muting circuit. .Iaddend.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a muting circuit for temporarily muting anaudio signal according to a muting operation and, more particularly, toa muting circuit in which such noise as click sounds that may otherwiseaccompany the switching operation for muting are eliminated.

2. Description of the Prior Art

The muting circuit is generally used for such purposes as deletingcommercial announcements or commentary inserted between consecutivepieces of music, for instance, when recording an FM music program. In awell-known muting circuit, a switch is connected between the audiosignal input and the output terminals and is turned on-off according toa muting signal.

In such a prior art muting circuit, however, the switch is turned on-offsimultaneously with the appearance of the muting signal (or level changethereof), that is, the audio signal is muted and demuted even when thewaveform level of the audio signal (i.e., instantaneous amplitudethereof) is not at a zero level, thus giving rise to noises such asclick sounds.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an improved mutingcircuit which can overcome the aforedescribed drawback inherent in theprior art.

A more specific object of the present invention is to provide a mutingcircuit, in which the generation of the aforementioned noise isprevented in that the switching operation for muting is brought about atan instant when the instantaneous level of the audio signal waveformbecomes zero.

A further object of the present invention is to provide a mutingcircuit, in which the switching operation is forcibly effected formuting in case the aforementioned zero level is not detected within afixed period of time from the instant of change of the muting signal.

To attain the above objects, the muting circuit according to the presentinvention includes a muting control circuit, which controls the on-offoperation of a switching circuit connected between an input terminal andan output terminal according to a muting signal, more particularly itdetects the waveform level of the input audio signal and causes theswitching operation of the switching circuit according to the mutingsignal at an instant when the waveform level approaches a zero level.The muting control circuit may also be adapted to cause the switchingoperation of the switching circuit on the basis of the relationshipbetween the time elapsed from the instant of change of the muting signaland the input signal waveform level.

The above and other objects, features and effects of the presentinvention will become more apparent from the following detaileddescription of the present invention and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C show a time chart illustrating the relation between inputaudio signal and muted output audio signal.

FIG. 2 is a block diagram showing a first embodiment of the presentinvention; and

FIG. 3 is a circuit diagram showing a second embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIGS. 1A to 1C show the relation between input audio signal and mutedoutput audio signal. When muting is effected on the input audio signalas shown in FIG. 1A at an instant when the waveform of the input signaldoes not cross the zero axis, such as at an instant T_(M), the outputaudio signal from a prior art muting circuit is suddenly reduced to thezero level at the instant T_(M) as shown in FIG. 1B. Therefore, thewaveform becomes discontinuous, thus resulting in click noises.

This invention has been intended to prevent such a sudden change of thewaveform by permitting the muting to be effected in effect at theinstant T_(S), at which time the level of the input signal waveformitself becomes zero immediately after the instant T_(M), as shown inFIG. 1C.

FIG. 2 shows a block form of the basic construction of a firstembodiment of the present invention. In FIG. 2, an audio signal suppliedto an input terminal 2 of the muting circuit 1 is fed through aswitching circuit 3 for muting to an output terminal 4. The input signalappearing at the input terminal 2 is also supplied to a level detectingcircuit 6 in a muting control circuit 5. In the instant embodiment, themuting control circuit 5 includes a level detection circuit 6 and a timedetection circuit 7. A muting signal from a manually operable switch 8is supplied to the level detection circuit 6 and time detection circuit7. For example, when effecting the muting, the switch 8 is turned on toprovide a muting signal of "L" (low level). When releasing the muting,it is turned off to provide a "H" (high level) muting signal.

The level detection circuit 6 detects the level of the audio inputsignal waveform (instantaneous crest value) at the time of theaforementioned muting, and when the level approaches the zero level, forinstance becomes less than -60 dB, it supplies the muting control signalto the switching circuit 3 to render the circuit 3 into a cut-off state.Thus, if the muting mode is brought about in the presence of the audioinput signal at the input terminal 2 as shown in FIG. 1A, for instanceat the instant T_(M), the switching circuit 3 is turned off at aninstant T_(S) when the waveform of FIG. 1A is substantially zero. Inconsequence, an output signal as shown in FIG. 1C is provided from theoutput terminal 4. In this way, the generation of noise such as clicknoises can be prevented.

In case where the input signal to the input terminal 2 is an audiosignal or the like obtained through a direct current amplifier, thereference level is likely to deviate from the ground level. In such acase, it is likely that the instantaneous level at each point of thesignal waveform is not at a zero level in the case when the input signallevel is low. At the instantaneous level which is other than zero, theswitching circuit 3 is not turned off even when the muting mode occurs.To preclude this inconvenience, according to the present invention thetime detection circuit 7 is provided within the muting control circuit5. This time detection circuit 7 is adapted to provide a muting controlsignal to the switching circuit 3 to forcibly turn off the switchingcircuit 3 after the lapse of a constant period of time, for instance 100msec., from the instant of a change of the muting signal from the switch8, for instance from the "H" to the "L" level. With this arrangement,the muting operation, i.e., the turning-off of the switching circuit 3,is effected even if the zero level is not detected due to causes such asvariations of the reference level of the input audio signal.

While the above description has been for the case of muting, that is,bringing about the muting mode, in the case of releasing the muting(i.e., muting-off), the audio signal also appears from the outputterminal 4 from the instant when the input signal waveform crosses zerolevel, and also the muting is forcibly released after a constant periodof time.

Further, the detection level may be increased from zero level with thelapse of time from the instant of change of the muting signal. In such acase, the muting operation can be effected even at a high level suchthat some time elapses. Further, the muting can be readily accomplishedat desired levels and times.

FIG. 3 shows a block diagram of a second embodiment of the presentinvention applied to a muting circuit 11 for muting a digital audiosignal such as a PCM audio signal. In FIG. 3, a PCM audio signal, forinstance with each word of 14 bits, is supplied to the input terminal12. Here, a single amplitude value when an analog audio signal issampled under the control of a predetermined sampling signal (forinstance at 44 kHz) corresponds to one word, and this amplitude value isconverted into a 14-bit data, for instance by the method of displayingthe complement of 2, to provide the PCM signal where one word consistsof 14 bits. This PCM audio signal of the embodiment is a serial datasignal where left and right channel data of a stereo audio signal arealternately arranged one word after another on the time axis byalternately sampling the left and right channels of the signal, only thedata of either left or right channel can be taken out through gatingcontrol with, for instance, a signal at the sampling frequency (forinstance 44 kHz) and at a duty ratio of 50%.

The PCM audio signal supplied as an input signal to the input terminal12 is coupled through the switching circuit 13 for muting to the outputterminal 14. The input signal is also coupled through an exclusive ORcircuit (hereinafter referred to as Ex.OR circuit) 21 to a leveldetection circuit 16. To the other input terminal of the Ex.OR circuit21 is supplied to the Q output from a latch circuit which uses, forinstance, a D type flip-flop. To a latch signal input terminal of thelatch circuit 22, a one-word period pulse from a word reset outputcircuit 23 at an instant corresponding to the first bit of one wordmentioned above (or common terminal MSB) is supplied to latch the MSB ofone word of the input data. The content of the MSB is either "0" or "1"representing the positive or negative symbol in the case of theaforementioned display of the complement of 2. Thus, the output datafrom the Ex.OR circuit 21 is a pure binary data representing theabsolute value of the input data regardless of whether the input data ispositive or negative.

In the level detection circuit 16, the output data of the Ex.OR circuit21 is supplied through an OR circuit 24 to a data input terminal of a Dtype flip-flop 25, and the Q output therefrom is fed back to theaforementioned OR circuit 24. A word bit clock (hereinafter referred toas WBC) is supplied to a clock input terminal of the D type flip-flop25, and the pulse output of the aforementioned word reset output circuit23 is supplied to the reset or zero clear input terminal CL of the Dtype flip-flop 25. Thus, when the successive bit contents of one word ofthe input data from the MSB are all "0", the Q output is "0," but evenif a single one bit is "1," this data content of "1" is fed back throughan OR circuit 24 to the data input terminal, and consequently the Qoutput remains "1" until it is reset at the time of the appearance ofthe MSB of the next word. The Q output is "1" until the appearance of a"1" content bit from the MSB of one word, and after the appearance ofthis "1" content bit it subsequently continues to be "0".

In the case of the PCM data where one word consists of 14 bits, the10-th bit substantially corresponds to -60 dB, and whether the level ofthe original waveform of the input PCM data is below -60 dB can bedetermined from the Q or Q output at the instant of the appearance ofthe 10-th bit. For this reason, the Q output of the D type flip-flop 25is coupled through an OR circuit 26 to a judgement latch circuit 27, anda pulse corresponding to the 10-th bit of one word is supplied from apulse output circuit 29 to a latch input terminal of the judgement latchcircuit 27. Thus, when it is detected that the input data is below -60dB, the Q output from the judgement latch circuit 27 becomes "1." Thejudgement latch circuit 27 may be a D type flip-flop, and the pulseoutput from the word reset output circuit 23 is supplied to its clearinput terminal.

The Q output of the judgement latch circuit 27 is supplied to a channelseparation circuit section 30 which is provided for permitting themuting to be effected independently for the left and right channels. Inthe channel separation circuit section 30, the aforementioned Q outputis supplied to two NAND circuits 31 and 32, and a rectangular wave at 44kHz and with a duty ratio of 50% is supplied in the opposite phaserelation (i.e., with 180° phase difference) to the other input terminalsof the NAND circuits 31 and 32. This can be done by supplying a 44-kHzrectangular wave with a duty ratio of 50% appearing at a terminal 33directly to the NAND circuit 32 and also through an inverter 34 to theNAND circuit 31.

The outputs of the NAND circuits 31 and 32 are supplied to latch pulseinput terminals of latch circuits 35 and 36. The muting signal issupplied to the data input terminals of these latch circuits 35 and 36.It is obtained by supplying a signal from a manually operable switch(not shown) through an input terminal 28, an inverter 37 for waveformshaping and a latch circuit 38, and its "1" level corresponds to themuting-on, and its "0" level to the muting-off. This muting signal islatched in the latch circuits 35 and 36 according to the output pulsesfrom the NAND circuits 31 and 32.

The Q outputs from the latch circuits 35 and 36 are coupled torespective NAND circuits 41 and 42 in the aforementioned switchingcircuit 13 for muting. A rectangular wave signal at 44 kHz and with aduty ratio of 50% from an input terminal 43 is supplied to the NANDcircuit 42 directly and to the NAND circuit 41 after inversion throughan inverter 44, that is, it is supplied in the opposite phase relationto the NAND circuits as in the channel separation circuit section asmentioned above. However, the signal 44K' supplied to the input terminal33 of the channel separation circuit section 30 leads in phase by 90°the signal 44K supplied to the input terminal 43 of the switchingcircuit 13. The outputs of the NAND circuits 41 and 42 constitute twoinputs to a NAND circuit 45 which uses an OR circuit providing negationon the input side. In this case, the same effects may also be obtainedby using AND circuits for the first stage NAND circuits 41 and 42 and ORcircuits for the second stage NAND circuit 45. The output of the NANDcircuit 45 is supplied to an AND circuit 46 to control the data signalsupplied from the input terminal 12 to the AND circuit 46.

Thus, at the time of muting-on with the manual operation of the mutingswitch (not shown), a signal "1" is supplied to the data input terminalsof the latch circuits 35 and 36. At this time, the input data signalsupplied to the input terminal 12 is level detected for each word(corresponding to one sampled value) by the level detection circuit 16,and whether the bits from the MSB of one word up to the 10-th bit(corresponding to -60 dB) are all "0" is checked by the level detectioncircuit 16 and judgement latch circuit 27. When the bits up to the 10-thbit mentioned above are all "0," the Q output of the judgement latchcircuit 27 becomes "1" and is supplied to the NAND circuits 31 and 32 ofthe channel separation circuit section 30 as such. The NAND circuits 31and 32 operate complementarily with respect to each other depending uponwhether the relevant word of the input data signal is of the left orright channel. When a level below -60 dB is detected with respect to thedata of a left channel word, a latch pulse is supplied from the NANDcircuit 31 to the latch circuit 35, whereby "1" is latched as the mutingsignal. The Q output of the latch circuit 35 (which is "0" after theaforementioned latching) is supplied to the NAND circuit 41 of theswitching circuit 13, and is coupled through the NAND circuit 45 to theAND circuit 46 in synchronism to the word switching timing of the inputdata signal. After the aforementioned latching, the output of the NANDcircuit 45 is "0" only for the left channel word period, and the outputdata signal supplied from the AND circuit 46 to the output terminal 14is muted such that all the left channel word bits are zero.

It is of course to be understood that the muting is similarly effectedfor the right channel when the right channel word content corresponds toa level lower than -60 dB.

A time detecting circuit 17 is provided for forcibly effecting themuting after the lapse of a constant period of time from the instant ofchange of the muting signal mentioned above (i.e., from the instant ofchange from "0" to "1" or from "1" to "0"). To detect the change ofsignal accompanying the muting operation coupled to the input terminal28, the input and the output signals to and from, for instance, thelatch circuit 38 are supplied to the Ex.OR circuit 48. The output of theEx.OR circuit 48 is coupled through an inverter 49 to the clear terminalCL of a time counting circuit 47, and the output signal of "1" from thetime counting circuit 47 is supplied to the OR circuit 26. The timecounting circuit 47 may be constructed using a shift register, throughwhich the input data can be progressively shifted according to a clockpulse signal of a constant cycle period (for instance 16 msec.). With an8-bit shift register, a measurable time range up to 128 msec. can beprovided. In other words, if the aforementioned zero level (i.e., levelbelow -60 dB) is not detected until a period of 128 msec. has elapsedfrom the instant when the muting mode is brought about, the output "1"of the time counting circuit 47 is coupled through OR circuit 26 to thejudgement latch circuit 27 to forcibly effect the muting operation asdescribed previously.

In the instant embodiment, the detection of overflow is simultaneouslymade when the peak of the aforementioned waveform level or data exceeds14 bits.

More particularly, a binary data representing the absolute value of theinput data from the Ex.OR circuit 21 is supplied through an inverter 51to an OR circuit 52 of the peak detection circuit 19, and in the peakdetection circuit 19 whether "1" is present as a bit content in one wordis detected through the feedback of the output of the OR circuit 52through a latch circuit 53 to the OR circuit 52. This corresponds to thedetection as to whether "0" is present in the bit content of one word asthe output data from the Ex.OR circuit 21, and if a "0" bit is detected,the Q output of the latch circuit 53 is subsequently held at "1." The Qoutput of the latch circuit 53 is supplied to a peak judgement latchcircuit 54, to which a latch pulse is supplied from a pulse outputcircuit 29 for the 14-th bit of one word. Thus, when the output datafrom the Ex.OR circuit 21 up to the LSB (i.e., 14-th bit) are all "1,"the Q output of the judgement latch circuit 54 becomes "1," and a peakdetection signal (or overflow detection signal) is supplied through thechannel separation circuit section 56 to the output terminal 55. Thechannel separation circuit section 56 includes two NAND circuits 57 and58 and an AND circuit 59. The two NAND circuits 57 and 58, like theaforementioned channel separation circuit section 30, are gatecontrolled by 44-kHz opposite-phase rectangular signals.

As has been described in the foregoing, the muting circuit according tothe present invention comprises a switching circuit connected betweeninput and output terminals and a muting control circuit for controllingthe switching operation of the switching circuit according to the mutingsignal, and the waveform level of the input signal from the inputterminal is detected and the switching operation of the switchingcircuit is caused according to the muting operation at an instant when azero level is approached by the muting signal.

Thus, in contrast to the prior art muting circuits in which click noisesor other noise results from the fact that the muting is brought about atan instant when the signal waveform is not zero as shown in FIG. 1B,with the construction according to the present invention the muting isbrought about at an instant when the signal waveform crosses the zerolevel as shown in FIG. 1C, thus eliminating the generation of theaforementioned noise.

Another feature of the present invention resides in that the mutingcontrol circuit in the muting circuit having the aforementioned featurecauses the switching operation of the switching circuit on the basis ofthe relation between the time elapsed from the instant of change of themuting signal and the waveform level of the input signal.

Thus, even in case when the zero level detection cannot be made in casewhen a direct current level is introduced into the input audio signal,the muting can be forcibly brought about or released.

The above embodiment of the present invention is by no means limitative,and various changes and modifications can be made without departing fromthe scope and spirit of the present invention.

What is claimed is:
 1. A digital muting circuit comprising, an inputterminal .[.for.]. receiving a PCM signal having words of plural bits,an output terminal .[.for.]. deriving said PCM signal, a controllingcircuit .[.for.]. generating a muting signal, a detecting circuit forexamining the bit pattern of said PCM signal to produce a detectedsignal when the signal level of the waveform corresponding to said PCMsignal is less than a predetermined value, and switching means connectedbetween said input terminal and said output terminal and .[.for.].replacing said PCM .Iadd.output .Iaddend.signal with a PCM signal havinga bit pattern representing the zero level by receiving said detectedsignal while said muting signal is generated.
 2. A digital mutingcircuit according to claim 1, further comprising time counting means.[.for.]. counting a predetermined time elapsed from the instant ofchange of said muting signal and .[.for.]. producing a switching signalso as to cause the switching operation of said switching means on thebasis of the relationship between the time elapsed from the instant ofchange of said muting signal and the waveform level of said inputsignal. .Iadd.
 3. A digital muting circuit comprising, an input terminalreceiving a PCM signal having words of plural bits, an output terminalderiving said PCM signal, a controlling circuit generating a muting-offsignal, a detecting circuit examining the bit pattern of said PCM signalto produce a detected signal when the signal level of the waveformcorresponding to said PCM signal is less than a predetermined value, andswitching means connected between said input terminal and said outputterminal and replacing a PCM output signal having a bit patternrepresenting the zero level with said PCM signal by receiving saiddetected signal when said muting-off signal is generated..Iaddend..Iadd.4. A digital muting circuit according to claim 3, furthercomprising time counting means counting a predetermined time elapsedfrom the instant of change of said muting-off signal and producing aswitching signal so as to cause the switching operation of saidswitching means on the basis of the relationship between the timeelapsed from the instant of change of said muting-off signal and thewaveform level of said input signal..Iaddend.